The present invention concerns a method for generating widths for segments of power busses (nets) in integrated circuits.
Within an integrated circuit, power nets are used to provide current to logical circuitry. Power nets are networks of wires which carry a power voltage or a ground voltage to the logical circuitry of an integrated circuit. When placing and sizing power nets, it is desirable to minimize the space the power nets use on the integrated circuit. However, it is also necessary that the power nets provide sufficient current so that during switching of logic circuitry, the voltage on the power nets will remain within a designated voltage range. Further, the power nets must be of significant width so that electromigration does not affect circuit performance.
Power routers are used to route power nets on an integrated circuit. For examples of existing power routers, see M. Beardslee, J. Burns, A Casotto, M. Igusa, F. Romeo, and A. Sangiovanni-Vincentelli, Mosaico: An Integrated Macro-Cell Layout System, MCNC International Workshop on Placement and Routing, 1988, Session 6.1; S. Chowdhury, Optimum Design of Reliable IC Power Networks Having General Graph Topologies, Design Automation Conference, 1989, pp. 787-790; or W-M Dai, H. H. Chen, R. Dutta, M. Jackson, E. S. Kuh, M. Marek-Sadowska, M. Sato, D. Wang, and X-M Xiong, BEAR: A New Building-Block Layout System, Int'l Conference on Computer Aided Design, 1987, pp. 34-37. Modern technologies, however, continue to allow the design of larger integrated circuits with increasingly higher gate densities, faster operating frequencies and have higher power dissipation. Since power nets often occupy more than ten percent of available circuit area, it is desirable to develop techniques which allow reduction in the size of power nets without sacrificing circuit performance.